> > them or let reads pass writes. [thus, a readl() will cause a PCI flush
> > of all delayed writes]
>
> This would assume that the CPU itself does not reorder reads and writes?
We define readl() to be strictly ordered. Thats a kernel decision. The
__readl() is not neccessarily strictly ordered. Use __readl() with care.
> processors which Linux currently supports do external read/write
> reordering? If so, would this alter the order as seen by the PCI
> bridge?
PowerPC at least can do this, but see above
> Suppose, for example, that the CPU writes two words to memory. Does the
> PCI DMA see them in the correct order (non-Pentium), or must some
> special barriers be used?
This is defined in the PentiumII manuals.
> What happens the PCI DMA wants to write to an address which is currently
> dirty, within a CPU cache?
The PCI write is stalled, the cache line written back and invalidated, then
the data is written
> What happens when PCI DMA wants to read an address which is currently
> dirty, within a CPU cache?
Pretty much the same.
> What happens when PCI DMA writes to an address which is currently clean
> within a CPU cache?
It goes dirty
The memory bus stuff is defined in the intel docs not the PCI docs. On
a PowerPC for example I believe the answer to most of the above questions
is 'you lose'. That is why we have pci_alloc_consistent and the like to avoid
spending all day flushing caches.
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This archive was generated by hypermail 2b29 : Sat May 20 2000 - 18:35:05 EDT