Andrew Morton <andrewm@uow.edu.au> writes:
> We know that Pentium uses 'processor order'.
Yes, but processor ordering only applies when the write-back memory
type is in effect. MMIO is most often done through uncached memory, so
(accoding to the Intel docs) all reads and writes appear in-order on
the processor bus. (Even with this, I suppose it's possible for the
chipset to coalesce transactions, but I haven't read that any Intel
chipsets do so)
The memory types become gradually more relaxed as you go from uncached
to write combining to write through to write back. At least for P6
processors. (Pentium is similar, I think, but I haven't read the
Pentium-era Intel docs as thoroughly)
David Wragg
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