On Mon, 22 May 2000, Alan Cox wrote:
> > > Then my 386 breaks. Sorry you lose. My 386 is AT compatible your system
> > > is broken.
> >
> > No, no, your 386 does not break. This is absolute diatribe.
>
> You want to come here and see. My old 386 box requires the delays when
> accessing the timer chip otherwise it is erratic. My old 386 is AT compatible.
> It has the odd fit if you touch the interrupt controller fast too.
>
This is not the timer chip.
> We have recent technology DEC laptops that require timing delays on the
> keyboard controllers are honoured for that matter
>
This is not the keyboard controller.
> You might suggest using udelay() here but unfortunately we cannot calibrate
> udelay until the TSC is programmed so that is out too.
>
This is not necessary. Although "xor cx,cx ; loop $" will satisfy
pedantics during the one-time setup of the chip.
> The timer setup is the one place where 'switch to udelay' isnt the answer. I
> wish it was because I would be glad to use udelay() there ot help.
>
I'm not asking for changes in the timer-chip setup.
> [Not that it does help because an IRQ during the setup will randomly break
> the programming - I assume AMD thought of that ???]
>
The IRQ, if it happens, will break everything anyway. You can't do
out 0x20, 0x11 ; Start setup sequence
... get interrupted
out 0x20, 0x20 ; ISR sends EOI to controller.
... so this is not relavant. The mask registers, 0x21, and 0xA1 have
been masked off in setup.S anyway.
> Alan
>
Cheers,
Dick Johnson
Penguin : Linux version 2.3.41 on an i686 machine (800.63 BogoMips).
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This archive was generated by hypermail 2b29 : Mon May 22 2000 - 09:11:02 EDT