On Thu, 27 Jul 2000 19:16:41 -0700,
"Linda Walsh" <law@sgi.com> wrote:
>Cache lines on the MIPS-NUMA use a 128-byte (not bit) cache line,
>so for optimal performance, you'd want you weren't sharing
>that cache line w/any other frequently used/modified data.
>Now how to guarantee proper cache alignment on a given
>platform....hmmm
Like this. No need for a pad field, gcc automatically pads the
structure to the correct size.
typedef struct {
unsigned int __local_irq_count;
unsigned int __local_bh_count;
unsigned int __nmi_counter;
} ____cacheline_aligned irq_cpustat_t;
____cacheline_aligned is defined in linux/cache.c.
#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
SMP_CACHE_BYTES defaults to L1_CACHE_BYTES. L1_CACHE_BYTES is defined
in asm/cache.c; some arch's hard code it, others pick it up from a
CONFIG variable which depends on the machine type.
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This archive was generated by hypermail 2b29 : Thu Jul 27 2000 - 22:32:25 EDT