Hi!
I've noticed that the 1.9 driver didn't make it into test8-pre1, even
with Andre's blessing. So I decided to delve deeper into it and hunt for
any possible remaining problem cases in it. Checked against the
ATA/ATAPI 1-6 specs, too. It should get the timing correct on every
chipset and bus clock for every drive now.
Changes since 1.9:
* Rewrote the timing code to always generate timings within the ATA
spec. Compliance can be checked in /proc/ide/via. There could be cases
in the 1.9 driver where the speed would be a little faster than ATA
allows. The present in-kernel driver gets the timing completely wrong
(too fast) for MWDMA0, btw. This is the most important change.
* Added 80-wire ribbon cable detection. This is currently only based on
BIOS settings of the chipset, and thus very conservative, (If the BIOS
thinks UDMA4 (66 MB/sec) is OK, and both the drives agree, only then
it is enabled.) It can be manually set to UDMA4, for the case where
the test is too conservative.
* Added UDMA5 (100 MB/sec) to the tables, although currently supported
chipsets can't do it. However, if PCI is overclocked to 41.5 MHz,
UDMA5 can be *manually* turned on to deliver 83 MB/sec transfer rate.
This is within UDMA5 spec for the drive. It is not recommended, but
possible for those striving for max performance.
* Added PIO5 support. PIO5 is a nonstandard (not in ATA spec) mode some
drives support. It will be autodetected if the drive supports it.
* Added SWDMA support. This is unfortunately untested, because I don't
have any device able to do SWDMA. This is for the rare devices out
there that can't do MWDMA but you'd still like to run them in BMDMA
mode.
All in all, the new driver should be robust, ATA-spec compliant, easy to
use and tuned for maximum preformance. In that order.
I'm submitting it for inclusion in test8-pre2.
TIA.
-- Vojtech Pavlik SuSE Labs
This archive was generated by hypermail 2b29 : Tue Aug 29 2000 - 05:43:46 EDT