RE: Updated 2.4 TODO List - more on PCI resources...]

From: Dunlap, Randy (randy.dunlap@intel.com)
Date: Fri Oct 13 2000 - 17:22:32 EDT

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    I'm not familiar with yenta controllers/devices,
    and I'm not trying to throw you a tasty red herring,
    but...

    yenta_config_init() does
        config_writeb(socket, PCI_CACHE_LINE_SIZE, 32);

    Is this writing to the CardBus bridge or to the device's
    CacheLineSize register?

    If the latter, and given that PCI_CACHE_LINE_SIZE is in
    units of 4-byte "words", is 32 [= 128 bytes] a good value
    to use? If so, why?

    Or is it OK because it is setting a PCI bridge device's
    cache line size?

    From TI's PCI1451 GJG CardBus controller spec:
    4.8 Cache Line Size Register
    The cache line size register is programmed by host software to indicate
    the system cache line size.

    Thanks,
    ~Randy

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