About Celeron processor memory barrier problem

From: michael chen (linux-kernel@vger.kernel.org)
Date: Thu Dec 23 1999 - 04:24:43 EST

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    Hi,
            I found that when I compiled the 2.4 kernel with the option
        of Pentium III or Pentium 4 on a Celeron's PC, it could cause the
        system hang at very beginning boot stage, and I found the problem
        is cause by the fact that Intel Celeron doesn't have a real memory
        barrier,but when you choose the Pentium III option, the kernel
        assume the processor has a real memory barrier.
        Here is a patch to fix it:

        Merry Christmas :)
        Michael Chen

    diff -Nur linux/include/asm-i386/system.h linux.new/include/asm-i386/system.h
    --- linux/include/asm-i386/system.h Mon Dec 11 19:26:39 2000
    +++ linux.new/include/asm-i386/system.h Sat Dec 23 16:06:01 2000
    @@ -274,7 +274,14 @@
     #ifndef CONFIG_X86_XMM
     #define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
     #else
    -#define mb() __asm__ __volatile__ ("sfence": : :"memory")
    +#define mb() do { \
    + if ( cpu_has_xmm ) { \
    + asm volatile("sfence": : :"memory"); \
    + } \
    + else { \
    + asm volatile("lock; addl $0,0(%%esp)": : :"memory"); \
    + } \
    +} while (0)
     #endif
     #define rmb() mb()
     #define wmb() __asm__ __volatile__ ("": : :"memory")
    diff -Nur linux/include/linux/tqueue.h linux.new/include/linux/tqueue.h
    --- linux/include/linux/tqueue.h Sat Dec 23 16:16:44 2000
    +++ linux.new/include/linux/tqueue.h Sat Dec 23 16:06:01 2000
    @@ -17,6 +17,7 @@
     #include <linux/list.h>
     #include <asm/bitops.h>
     #include <asm/system.h>
    +#include <asm/processor.h>
     
     /*
      * New proposed "bottom half" handlers:
    diff -Nur linux/include/asm-i386/system.h linux.new/include/asm-i386/system.h
    --- linux/include/asm-i386/system.h Mon Dec 11 19:26:39 2000
    +++ linux.new/include/asm-i386/system.h Sat Dec 23 16:06:01 2000
    @@ -274,7 +274,14 @@
     #ifndef CONFIG_X86_XMM
     #define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
     #else
    -#define mb() __asm__ __volatile__ ("sfence": : :"memory")
    +#define mb() do { \
    + if ( cpu_has_xmm ) { \
    + asm volatile("sfence": : :"memory"); \
    + } \
    + else { \
    + asm volatile("lock; addl $0,0(%%esp)": : :"memory"); \
    + } \
    +} while (0)
     #endif
     #define rmb() mb()
     #define wmb() __asm__ __volatile__ ("": : :"memory")
    diff -Nur linux/include/linux/tqueue.h linux.new/include/linux/tqueue.h
    --- linux/include/linux/tqueue.h Sat Dec 23 16:16:44 2000
    +++ linux.new/include/linux/tqueue.h Sat Dec 23 16:06:01 2000
    @@ -17,6 +17,7 @@
     #include <linux/list.h>
     #include <asm/bitops.h>
     #include <asm/system.h>
    +#include <asm/processor.h>
     
     /*
      * New proposed "bottom half" handlers:

    -
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